Random pattern generators for generating sequences or patterns of numbers are well known. Random pattern generators are commonly used in data processing and digital signal processing applications such as data encryption, data communications and system testing. For example, random pattern generators are commonly used in testing logic circuits. Accurate and complete testing of a logic circuit is necessary to ensure the functional integrity of the circuit. Random pattern generators are often utilized to generate the necessary test patterns and sequences.
It has heretofore been found that many logic circuits are "resistant" to random pattern testing. For these circuits, in order to achieve complete testing, i.e. obtain high fault coverage, an extremely large number of random patterns must be generated. The simple example of a common "AND" gate having ten inputs illustrates the resistance of a logic circuit to random pattern testing. In order to ensure the functional integrity of the ten input "AND" gate, all ten inputs must have a binary value of ONE. In order to guarantee that a test pattern will be generated having all ten bits with a binary value of ONE, 2.sup.10 random patterns must be generated because each bit of a random pattern will have a binary value of ONE half the time and a binary value of ZERO half the time. This is an extremely large number of test patterns for a single gate. As the complexity of the circuit increases, so does the number of necessary test patterns.
Alternatively, one can forego testing with random patterns and utilize algorithmically generated test patterns. For example, a ten input "AND" gate can be tested in as few as eleven test patterns. However, generation of test patterns with an algorithm, given a circuit structure, is often considered a more difficult task than generating randomly generated test patterns in order to attain the same fault coverage.
The art has heretofore solved this problem by "weighting" the patterns produced by a random pattern generator. Weighting is the technique of generating a random pattern which is slanted or biased toward a desired value. In a weighted random pattern, each bit occurs in a random fashion, but the long term distribution of the bits will not approach an equal distribution of ONEs and ZEROs, but rather will approach a predetermined unequal distribution of ONEs and ZEROs. The resulting weighted pattern will test the inaccessible internal circuit elements. In other words, weighting is the process whereby patterns are biased so that a greater number of ZEROs or a greater number of ONEs may be applied to the inputs of a system being tested, resulting in an increased likelihood of detecting errors in the system.
One known weighted random pattern generation apparatus and method is described in a series of patents assigned to IBM Corporation. See U.S. Pat. No. 4,688,223 to Motika et al.; U.S. Pat. No. 4,687,988 to Eichelberger et al.; U.S. Pat. No. 4,745,355 to Eichelberger et al.; and U.S. Pat. No. 4,801,870 to Eichelberger et al., all of which are entitled Weighted Random Pattern Testing Apparatus and Method. These IBM patents employ a technique for determining the functionality of the system to be tested and individually weighting the test patterns placed upon this system in order to bias the components of the individual test patterns in favor of more or less binary ONEs or ZEROs.
The weighted random pattern generator of the IBM patents is comprised of a random pattern generator of the linear feedback shift register configuration, a weighting circuit having a plurality of cascaded "AND" gates, and a multiplexor. The first five bits of the shift register are the only random bits used and are connected to the cascaded "AND" gates. The first bit is connected directly to the multiplexor as well as one input of the first "AND" gate. Each successive random bit of the five are input to a successive one of the "AND" gates. The second input to the second, third and fourth "AND" gates are the outputs of the preceding gate. In addition to being inputs for successive "AND" gates of the weighting circuit, these outputs are also inputs to the multiplexor. The series of gates causes the probability of producing a binary ONE at each successive output to be one half that of producing a binary ONE at the preceding output. Thus the probabilities are one-half, one-fourth, one-eighth, one sixteenth, and one-thirty-second.
The multiplexor acts as a weight selector. The two control inputs to the multiplexor, i.e. a selector and a gating clock respectively, select the weight (input) to be used and provide the timing to gate the selected weight (input) through the multiplexor. The gating through of the weights occurs every first, second, third, fourth, or fifth shift (clock cycle) depending on whether the original bit comes from the first, second, third, fourth, or fifth bit location of the linear feedback shift register. Finally, the weight selected can be controlled so as to determine whether binary ZEROs or ONEs are to have the greater weight.
A major problem with the IBM weighting circuit is that all possible weights are not obtainable in that the set of possible weights is restricted to {1/2.sup.k, 1/2.sup.k-1, . . . 1/2, . . . , 11/2.sup.k-1, 11/2.sup.k }, k=1, 2, 3 . . . , .infin.. In other words, regardless of the value for k, this means that weights in the ranges of (1/2, 1/4), (1/2, 3/4), (1/4, 1/16), {3/4, 15/16} and so forth can never be achieved. Furthermore, obtaining a low probability (one very close to zero) or a high probability (one very close to one) is very time consuming since k clock cycles are required to obtain a signal, i.e. output, with probability of 1/2.sup.k or 11/2.sup.k. Finally, each input to a circuit to be tested requires one weighted pattern generator. This results in a great deal of hardware overhead. Although increased precision could be obtained using this system, the hardware complexity would continue to increase.
U.S. Pat. No. 3,719,885 to Carpenter et al. entitled "Statistical Logic Test System Having A Weighted Random Test Pattern Generator" also describes a weighted random pattern generation system having a decoder which converts random patterns from binary to decimal producing a large number of weight variations in order to achieve a high fault coverage. This results in the number of test patterns being proportional to the circuit switching activity, i.e. the complexities of the hidden circuit logic.
The Carpenter et al. weight pattern generator consists of a random pattern generator, a bit decoder and a weighting circuit. The bit decoder operates as a binary to decimal decoder producing a large number of outputs. The weighting circuit provides a larger number of bits to those elements of circuit under test which require a greater number of test patterns to insure the functional integrity of that particular element. In essence, the weighting performed in Carpenter et al. simply provides a means for supplying certain circuit element inputs with a larger number of test bits than other inputs. The weighting combines outputs of the decoder based on the resistance a given element, i.e. circuit input, has to random pattern testing.
In order to ensure the functional integrity of a highly complex circuit using the Carpenter et al. system, it is necessary to generate an extremely large number of test patterns. Moreover, testing time will increase with the complexity of the circuit. Finally, it is not possible to modify the test patterns so as to achieve a certain probability of producing a given test pattern, to thereby decrease the number of test patterns necessary to insure the functionality of the circuit under test.
A system for obtaining test patterns having certain probabilities is also described by David et al. in U.S. Pat. No. 4,730,319 entitled "Device For Transforming The Occurrence Probability Of Logic Vectors And For The Generation Of Vector Sequences With Time Variable Probabilities." David et al. provides a scheme whereby the probability that a given test pattern must occur is determined. Each pattern is then loaded into memory a number of times proportional to the total number of memory locations based upon the probability the test pattern must occur. A random number generator, which inherently has an equal chance of producing any given result, generates the address of the memory location where the test pattern is stored. The probability of obtaining a given test pattern is dependent upon the number of times that the pattern has been loaded into memory. The probability of selecting a particular memory location is not affected.
Although David et al. permits probabilities to be allocated, this allocation is based upon a manual load of patterns into memory based upon desired probability of occurrence. The probability of selecting one test pattern over another is constant in that the probability of selecting each memory location is equal. The selecting technique does not permit any modification of the random pattern. Moreover, the David et al. testing scheme is inefficient because the test vectors are not generated by modifying a random pattern but rather are manually determined and then forced into selection using the probability. Due to the high labor intensity needed to accomplish this task, testing of complex circuits will be very time consuming.
In summary, while the prior art provides weighted random pattern generators for producing weighted test patterns or vectors, these weighted random pattern generators may require a large number of test vectors in order to obtain high fault coverage. The precision of prior art weighted random number generators is limited, so that any arbitrary probability cannot be readily generated. Prior art weighted random number generators employ complex hardware which, by definition, limits the speed of weighted random number generation. Modification of the random patterns is also difficult.